AES development in FPGA

The National Institute of Standards and Technology (NIST) created a new standard known as Advanced Encryption Standard (AES), with the objective of developing the Federal Information Processing Standard (FIPS) which specifies an encryption algorithm capable of protecting sensitive information to be used by the government of the United States. In October 2000, the NIST selected Rijndael as the algorithm proposed for the AES. The algorithm has a round shape made up by three uniform and non-reversible transformations which assures broadcast over the total set of fixed rounds and optimal non-linearity properties. This thesis presents an 8-bit FPGA implementation of the 128-bit block and 128 bit-key AES cipher.Reseña de la tesis presentada en 2006 por Mónica Cristina Liberatori para obtener el título de Magister en Redes de Datos (UNLP)Es revisión de: http://sedici.unlp.edu.ar/handle/10915/4101Facultad de Informátic

Cryptographic algorithms for communicating results from distributed electronic voting systems

Electronic voting systems are increasingly used in electoral processes ranging from specialized stand alone machines, up to complete paperless and remote voting system. Votes secrecy and confidence are necessary in any electoral process. Public or private key cryptographic systems can be used in LAN or WAN facilities. Low level cryptographic structures and basic algorithms are mentioned. Enhancement of security levels in distributed voting schemes, are shown based in concatenated operations before transmission. Finally, processing time reduction with specialized hardware and mixed cryptosystems are discussedVI Workshop de Procesamiento Distribuido y Paralelo (WPDP)Red de Universidades con Carreras en Informática (RedUNCI

AES development in FPGA

The National Institute of Standards and Technology (NIST) created a new standard known as Advanced Encryption Standard (AES), with the objective of developing the Federal Information Processing Standard (FIPS) which specifies an encryption algorithm capable of protecting sensitive information to be used by the government of the United States. In October 2000, the NIST selected Rijndael as the algorithm proposed for the AES. The algorithm has a round shape made up by three uniform and non-reversible transformations which assures broadcast over the total set of fixed rounds and optimal non-linearity properties. This thesis presents an 8-bit FPGA implementation of the 128-bit block and 128 bit-key AES cipher.Reseña de la tesis presentada en 2006 por Mónica Cristina Liberatori para obtener el título de Magister en Redes de Datos (UNLP)Es revisión de: http://sedici.unlp.edu.ar/handle/10915/4101Facultad de Informátic

Diseño y evaluación de arquitecturas de computadoras : Marta Bertrán Pardo y Antonio Guzmán Sacristán, Pearson Educación, Madrid, 2010

In the first paragraph of the Introduction of the book the authors say "The definition of computer architecture has generated many discussions since the emergence of what could be considered the first computer in 1943, the ENIAC". Later they add "The main idea of all the proposals made in this direction is the same: define of computer components in different levels of study to produce a hierarchical description and to facilitate their understanding and design”. The authors' goal is to provide a textbook (written in Spanish) that systematically collect the most important techniques of design and evaluation of computer architectures.Facultad de Informátic

Cryptographic algorithms for communicating results from distributed electronic voting systems

Electronic voting systems are increasingly used in electoral processes ranging from specialized stand alone machines, up to complete paperless and remote voting system. Votes secrecy and confidence are necessary in any electoral process. Public or private key cryptographic systems can be used in LAN or WAN facilities. Low level cryptographic structures and basic algorithms are mentioned. Enhancement of security levels in distributed voting schemes, are shown based in concatenated operations before transmission. Finally, processing time reduction with specialized hardware and mixed cryptosystems are discussedVI Workshop de Procesamiento Distribuido y Paralelo (WPDP)Red de Universidades con Carreras en Informática (RedUNCI

High Performance VLSI Signal Processing: Innovative Architectures and Algorithms : Volume I - Algorithms and Architectures. Edited by K. J. Ray LIU and Kung YAO. IEEE Press. 1998. ISBN 0-7803-3468-X

The book intends to address the important aspects of high-performance signal processing with a focus on the recent development of VLSI technology for signal processing. The editors collect much of all the research efforts and findings that have made high performance implementation of signal processing possible in the last decade in two volumes.Facultad de Informátic

RTL fast convolution using the mersenne number transform

VHDL is a versatile high level language for the specification and simulation of hardware components. Here a functional VHDL model is presented for performing fast convolution based on Mersenne's number theoretic transform. For filtering a rather long input sequence xn() we can decomposed it into a number of short segments, each of which can be processed individually. The output yn()then becomes a combination of partial convolutions. The superposition principle for linear operators is used here. Each partial convolution can be solved using the Discrete Fourier Transform (DFT) implementing a fast FFT (Fast Fourier Transform) algorithm. This DFT approach is the most popular. In this paper we use the Mersenne Number Transform (MNT) as an alternative for the DFT in the framework of a register transfer level (RTL) implementation of the filter operation. Even when the MNT does not have a fast algorithm it can be see that RTL in the natural level of abstraction for the implementation of the MNT. This work is conceived as part of an academic exercise in the use of VHDL for modeling a DSP algorithm all the way from the mathematical specification to the circuit implementation.Eje: Procesamiento distribuido y paralelo. Tratamiento de señalesRed de Universidades con Carreras en Informática (RedUNCI

RTL fast convolution using the mersenne number transform

VHDL is a versatile high level language for the specification and simulation of hardware components. Here a functional VHDL model is presented for performing fast convolution based on Mersenne's number theoretic transform. For filtering a rather long input sequence xn() we can decomposed it into a number of short segments, each of which can be processed individually. The output yn()then becomes a combination of partial convolutions. The superposition principle for linear operators is used here. Each partial convolution can be solved using the Discrete Fourier Transform (DFT) implementing a fast FFT (Fast Fourier Transform) algorithm. This DFT approach is the most popular. In this paper we use the Mersenne Number Transform (MNT) as an alternative for the DFT in the framework of a register transfer level (RTL) implementation of the filter operation. Even when the MNT does not have a fast algorithm it can be see that RTL in the natural level of abstraction for the implementation of the MNT. This work is conceived as part of an academic exercise in the use of VHDL for modeling a DSP algorithm all the way from the mathematical specification to the circuit implementation.Eje: Procesamiento distribuido y paralelo. Tratamiento de señalesRed de Universidades con Carreras en Informática (RedUNCI

Interleaving Scheduling Algorithm for SLM Transactions in Mode S Surveillance Radar

Mode S Secondary Surveillance Radar establishes selective and univocally addressed transactions with aircraft within its coverage while using efficiently the available budgets of time and energy. This benefits are key to supporting high-traffic density. A preliminary interleaving algorithm for the scheduling of Short Length Message transactions is presented and tested under a heavy load simulated scenario.IX Workshop Procesamiento de Señales y Sistemas de Tiempo Real (WPSTR)Red de Universidades con Carreras en Informática (RedUNCI

Una arquitectura para la transformada numérica de Mersenne

La convolución exacta de secuencias de números enteros es una de las operaciones más importantes del procesamiento digital de señales. Cuando se requiere exactitud no puede usarse el tradicional método de la DFT para acelerar el proceso de cálculo debido a los factores de peso trascendentes presentes en las transformadas de Fourier, La Transformada Numérica de Mersenne (MNT) es una alternativa a la aplicación directa de la convolución, que podría resultar en arquitecturas más simples (menos complejas) según se muestra en, En este trabajo se presenta un arquitectura simple que implementa la MNT, basada únicamente en registros de desplazamientos y sumadores en complemento a uno. Los registros de desplazamientos resuelven las multiplicaciones en forma cableada, representando así una complejidad de 0(1). Los sumadores complemento a uno son una variante carry look-ahead, los cuales presentan un retardo moderado y son fáciles de diseñar. La arquitectura aquí presentada ha sido descripta en VHDL y simulada